1. Field of the Invention
The present invention relates to a comparator circuit used in an analog-to-digital converter, and more particularly, to a low power consumption low kick-back noise comparator circuit for an analog-to-digital converter, which can significantly reduce kick-back noise generated in a signal input stage due to a signal regeneration method employed in a signal comparing operation and can efficiently reduce power consumption.
2. Description of the Related Art
In general, an analog-to-digital converter stands for an electronic circuit which converts an analog signal represented as an electrically continuous voltage with the lapse of time into an electrically discrete digital signal and outputs the converted digital signal.
FIG. 1 is a block diagram illustrating the configuration of a conventional analog-to-digital converter.
Referring to FIG. 1, an analog-to-digital converter includes a reference voltage generator 10, a pre-amplification stage 20, a comparator circuit 30, and a digital encoding unit and 50. The analog-to-digital converter receives an externally applied input analog signal A_IN and reference voltages REFT and REFB as input signals and outputs converted digital outputs B-OUT[N-1:0] as output signals.
The reference voltage generator 10 is composed of a resistor string which divides the reference voltages REFT and REFB into fine voltages through a number of steps. The reference voltages REFT and REFB are respectively applied to both ends of the resistor string.
The pre-amplification stage 20 is composed of amplifiers having one input terminals to which the externally applied input analog signal A_IN to be converted is applied and the other input terminals to which the reference voltages generated in the reference voltage generator 10 are applied. The pre-amplification stage 20 is configured to compare the reference voltages and the input analog signal A_IN and amplify the signals.
The comparator circuit 30 is connected to the output terminals of the pre-amplification stage 20, and is configured to compare the polarities of the output signals from the pre-amplification stage 20 and convert the analog signals outputted from the pre-amplification stage 20 into digital signals.
The digital encoding unit is composed of a latch section 40 and an encoder 50 which convert the output signals of the comparator circuit 30 into finally changed digital outputs and output optional N-bit (N is a natural number greater than 1) digital signals.
In the analog-to-digital converter, the comparator circuit 30 is regarded as an essential circuit component for converting analog signals into digital signals. Depending upon the performance of the comparator circuit 30, various performance indexes of the entire analog-to-digital converter, including resolution, speed, power consumption, etc. are determined.
FIG. 2 is a configurational view of the comparator circuit which employs a conventional signal regeneration method.
Referring to FIG. 2, the comparator circuit includes an input stage 60 and a signal regeneration stage 70. The digital signals converted in the signal regeneration stage 70 are outputted as an output signal OUT to the digital encoding unit 40 and 50 through a latch 80.
The input stage 60 includes two transfer transistors MNI0 and MNI1 having gate terminals to which input signals INP and INN amplified and outputted by the pre-amplification stage 20 are applied, one terminals which are directly connected to signal regeneration nodes a and b provided in the signal regeneration stage 70 and the other terminals which are commonly connected with each other, and a bias transistor having a gate terminal to which a bias voltage BIAS is applied, one terminal which is connected to the commonly connected terminals of the two transfer transistors MNI0 and MNI1 and the other terminal which is connected to a ground source.
In the signal regeneration stage 70, the signal regeneration nodes a and b for receiving the input signals INP and INN from the respective one terminals of the two transfer transistors MNI0 and MNI1 provided in the input stage 60 are directly connected to the input stage 60. The signal regeneration stage 70 includes two PMOS transistors MP0 and MP1 having one terminals which are respective connected to the signal regeneration nodes a and b, and two NMOS transistors MN0 and MN1 having one terminals which are respectively connected to output nodes R and S for outputting a difference between the two input signals INP and INN, converted into a digital signal.
The two PMOS transistors MP0 and MP1 have the one terminals which are connected to the signal regeneration nodes a and b and gate terminals which are cross-connected to the one terminals of the two PMOS transistors MP0 and MP1, and the two NMOS transistors MN0 and MN1 have the one terminals which are connected to the output nodes R and S and gate terminals which are cross-connected to the one terminals of the two NMOS transistors MN0 and MN1, whereby cross-coupled inverters are constituted.
The signal regeneration stage 70 further includes a PMOS transistor having a gate terminal to which a clock signal CLK is applied and source and drain terminals which are respectively connected to the signal regeneration nodes a and b so as to be applied with the input signals INP and INN.
Also, the signal regeneration stage 70 includes two transistors having gate terminals to which a complementary clock signal CLKB having a logic value complementary to the clock signal CLK is applied, one terminals to which the signal regeneration nodes a and b are connected and the other terminals to which the output nodes R and S are connected, and an NMOS transistor having a gate terminal to which the complementary clock signal CLKB is applied and source and drain terminals which are respectively connected to the output nodes R and S.
In the conventional signal regeneration method, in order to realize a quick signal comparing operation, a small difference between the input signals INP and INN is quickly converted into a digital signal by a positive feedback operation in the cross-coupled inverters which is performed for a time during which the complementary clock signal CLKB is in a logic low state.
However, when such a signal regeneration method is employed, although the quick operation speed of the comparator circuit can be achieved through quick signal sensing capability, a large amount of power is consumed to generate a high voltage level signal in the signal regeneration stage 70.
Also, in the comparator circuit using the conventional signal regeneration method, since the input stage 60 is directly connected to the signal regeneration nodes a and b, a large amount of current is introduced into the input stage 60 from the signal regeneration stage 70 during a signal regeneration process, whereby power consumption increases.
Moreover, in the case where the input stage 60 is directly connected to the signal regeneration nodes a and b of the signal regeneration stage 70 as described above, since the voltage changed to a high level in the signal regeneration nodes a and b is transferred to the input signals INP and INN of the comparator circuit by the parasitic capacitance present between the gates and the drains of the two transfer transistors MNI0 and MNI1 provided in the input stage 60, a problem is caused in that kick-back noise is induced so that the signals from the input stage 60 of the comparator circuit are likely to be distorted, whereby the performance of the analog-to-digital converter may deteriorate.
As a consequence, in the comparator circuit using the conventional signal regeneration method, although the quick signal comparing operation is possible, the application of the analog-to-digital converter adopting the comparator circuit using the conventional signal regeneration method cannot help but be limited to a circuit operating at a high speed, in which it is not necessary to consider power consumption, due to great power consumption and large kick-back noise.
Accordingly, in order to allow the analog-to-digital converter operating at a high speed to be widely used in various application fields, a comparator circuit having low power consumption and reduced kick-back noise is keenly demanded in the art.